Southern Blotting
In this Video, Mrs. Deepika Rathore , Asst. Professor, Biyani Group of Colleges is explaining about the Southern Blotting. This technique is used for detection of a specific DNA sequence in …
Faculty: Education B.Ed. II Year(III Semester) Model Papers Sr. No. Paper Name Question Paper Link 1 Knowledge & Curriculam Click Here 2 Contemporary Indian and Education Click Here
Faculty: Education B.Ed. I Year(I Semester) Model Papers Sr. No. Paper Name Question Paper Link 1 Child Development and Growing Up Click Here 2 Contemporary Indian and Education Click Here 3 …
Faculty: ARTS B.A. III Year(VI Semester) Model Papers Sr. No. Paper Name Question Paper Link 1 Economics Click Here 2 English Literature Click Here 3 Geography Click Here 4 Political Science …
In this Video, Mrs. Deepika Rathore , Asst. Professor, Biyani Group of Colleges is explaining about the Southern Blotting. This technique is used for detection of a specific DNA sequence in …
In this Video, Mrs. Deepika Rathore , Asst. Professor, Biyani Group of Colleges is explaining about the Southern Blotting. This technique is used for detection of a specific DNA sequence in DNA samples. Southern blotting combines transfer of electrophoresis-separated DNA fragments to a filter membrane and subsequent fragment detection by probe hybridization. After hybridization, excess probe is washed from the membrane and the pattern of hybridization is visualized on X-ray film by autoradiography in the case of a radioactive or fluorescent probe, or by development of color on the membrane if a chromogenic detection method is used.
Best Girls College in Jaipur Rajasthan | Top College in Jaipur Rajasthan
http://www.gurukpo.com/
In this Video, Monika Kiroriwal, Assistant Professor, Biyani Group of Colleges explains about the implementation of CMOS NOR Gate logic design. CMOS logic design made by pull-up and pull-down networks. Pull-up …
In this Video, Monika Kiroriwal, Assistant Professor, Biyani Group of Colleges explains about the implementation of CMOS NOR Gate logic design. CMOS logic design made by pull-up and pull-down networks. Pull-up network is made by using PMOS transistors and pull-down network using NMOS transistors. To design the CMOS NAND gate first take the compliment of the expression and then make the pull-up and pull-down networks using PMOS and NMOS transistors respectively. PMOS transistors are connected in series and NMOS transistors are in parallel and after combining these two networks final CMOS NOR gate is produced. Output is taken at the junction points and then verify the truth table of digital NOR gate.
