• June 13, 2024

MCA Fifth Semester Model Papers

Faculty: IT 2019 Sample Papers with Solutions Sr. No.  Paper Name  Question Paper Link  Solution Link 1.  Cloud Computing  Click Here  Click Here 2.  Analysis & Design of Algorithm  Click Here …

MCA Third Semester Model Papers

Faculty: IT 2019 Sample Papers with Solutions Sr. No.  Paper Name  Question Paper Link  Solution Link 1.  Java Technologies  Click Here  Click Here 2.  Web Technologies  Click Here  Click Here 3. …

MCA First Semester Model Papers

Faculty: IT 2019 Sample Papers with Solutions Sr. No.  Paper Name  Question Paper Link  Solution Link 1.  Discrete Mathematics  Click Here  Click Here 2.  Programming in C & C++  Click Here …

MSC (Biotechnology) Previous Year Model Papers

Faculty: Science 2019 Sample Papers with Solutions Sr. No.  Paper Name  Question Paper Link  Solution Link 1  Immunology, Virology and Pathogenesis  Click Here  Click Here 2.  Cell Biology  Click Here  Click …

MSC (Biotechnology) Final Year Model Papers

Faculty: Science 2019 Sample Papers with Solutions Sr. No.  Paper Name  Question Paper Link  Solution Link 1  Plant Biotechnology  Click Here  Click Here 2.  Genetic Engineering  Click Here  Click Here

In this Video, Monika Kiroriwal, Assistant Professor, Biyani Group of Colleges explains about the implementation of CMOS NOR Gate logic design. CMOS logic design made by pull-up and pull-down networks. Pull-up network is made by using PMOS transistors and pull-down network using NMOS transistors. To design the CMOS NAND gate first take the compliment of the expression and then make the pull-up and pull-down networks using PMOS and NMOS transistors respectively. PMOS transistors are connected in series and NMOS transistors are in parallel and after combining these two networks final CMOS NOR gate is produced. Output is taken at the junction points and then verify the truth table of digital NOR gate.

Author

Leave a Reply