Month: November 2015

In this Video, Monika Kiroriwal, Assistant Professor, Biyani Group of Colleges explains about the implementation of CMOS NOR Gate logic design. CMOS logic design made by pull-up and pull-down networks. Pull-up network is made by using PMOS transistors and pull-down network using NMOS transistors. To design the CMOS NAND gate first take the compliment of the expression and then make the pull-up and pull-down networks using PMOS and NMOS transistors respectively. PMOS transistors are connected in series and NMOS transistors are in parallel and after combining these two networks final CMOS NOR gate is produced. Output is taken at the junction points and then verify the truth table of digital NOR gate.